In data processor systems having multiple processors, devices must be employed to allocate cycle resources between processors. A resource manager performing this function by allocating cycle resources to a data processor can easily track some of these cycle resources. Cycles used for code execution, data direct memory access (DMA) cycle steals (cycles unavailable to the data processor because of competition for a common resource), and other hardware services are easily tracked and accounted for because they are either periodic or predictable. However, cycles stolen because of asynchronous accesses to cycle resources by a second processor (such as a host personal computer) are not as easily tracked or managed.
Traditionally, the cycles stolen by the second processor have been limited by having the second processor pace itself through software timing loops in which it is assumed that each access to the data processor "steals" a constant number of cycles. This approach provides a crude method of estimating the worst case cycle steal threshold. As a consequence, reduced data throughput, and unused cycle resources result. Moreover, because the software timing loops are usually based on the second processor's system clock, typically a host processor's system clock which is different from the data processor system clock, the host's software is often required to perform a calibration step in order to adjust the timing loop counts.
Therefore, there is a need in the art for circuitry and methods that allow the second processor to precisely and deterministically limit and track all cycles stolen from the data processor core. Such circuitry and methods would provide a device for obtaining the maximum data throughput for a given cycle resource allocation. The same circuitry and methods would also eliminate the necessity for the software running on the second processor to perform a calibration to adjust the software timing loop counts.